Method for speeding up boolean satisfiability

ABSTRACT

A method for transforming a tautology check of an original logic circuit into a contradiction check of the original logic circuit and vice versa comprises interpreting the original logic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logic operators; transforming the original circuit obtained from the interpreting, into a dual logic circuit enabled for a checking of contradiction in place of tautology and vice versa, by providing a set of switching rules configured to switch each respective one of the original logic operators INV, AND, OR, MAJ, XOR, XNOR, MIN into a respective switched logic operator INV, OR, AND, MAJ, XNOR, XOR, MIN; and complementing outputs of the original circuit by adding an INV at each output wire. The method further provides testing in parallel the satisfiability of the original logic circuit, and the satisfiability of the dual logic circuit with inverted outputs. Responsive to one of the parallel tests finishing, the other parallel test is caused to also stop.

TECHNICAL FIELD

The invention is in the field of logic circuits.

BACKGROUND

Inspecting the properties of logic circuits is pivotal to logicapplications for computers and especially to Electronic DesignAutomation (EDA) [1]. There exists a large variety of properties to bechecked in logic circuits, e.g., unateness, linearity, symmetry,balancedness, monotonicity, thresholdness and many others [2]. Basiccharacteristics are usually verified first to provide grounds for moreinvolved tests. Tautology and contradiction are the most fundamentalproperties in logic circuits. A check for tautology determines if alogic circuit is true for all possible input patterns. Analogously, acheck for contradiction determines if a logic circuit is false for allpossible input patterns. While investigating elementary properties,tautology and contradiction check are difficult problems, i.e.,co-NP-complete and NP-complete, respectively [3]. Indeed, both tautologyand contradiction check are equivalent formulation of the BooleanSATisfiability (SAT) problem [3]. In this scenario, new efficientalgorithms for tautology/contradiction check are key to push further theedge of computational limits, enabling larger logic circuits to beexamined.

Tautology and contradiction check are dual problems. One caninterchangeably check for tautology in place of contradiction byinverting all outputs in a logic circuit. In this trivial approach, thetwo obtained problems are fully complementary and there is no explicitcomputational advantage in solving one problem instead of the other.

In the present description, we show that exact logic inversion is notnecessary for transforming tautology into contradiction, and vice versa.We give a set of operator switching rules that selectively exchangetautologies with contradictions. A logic circuit modified by our rulesis inverted just if identically true or false for all inputcombinations. In the other cases, it is not necessarily the complementof the original one. In a simple logic circuit made of AND, OR and INVlogic operators, our switching rules swap AND/OR operator types. We givea set of rules for general logic circuits in the rest of this paper.Note that in this paper we mostly deal with single output circuits. Formulti-output circuits, the same approach can be extended by ORing(contradiction) or ANDing (tautology) the outputs that need to bechecked into a single one.

Parallel checking techniques are known from prior art. For example, onecan launch in parallel many randomized check runs on the same probleminstance with the aim to hit the instance-intrinsic minimum runtime [4]

SUMMARY OF THE INVENTION

The invention provides a method for transforming a tautology check of anoriginal logic circuit into a contradiction check of the original logiccircuit and vice versa. The method comprises interpreting the originallogic circuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV originallogic operators; transforming the original circuit obtained from theinterpreting, into a dual logic circuit enabled for a checking ofcontradiction in place of tautology and vice versa, by providing a setof switching rules configured to switch each respective one of theoriginal logic operators INV, AND, OR, MAJ, XOR, XNOR, MIN into arespective switched logic operator INV, OR, AND, MAJ, XNOR, XOR, MIN;and complementing outputs of the original circuit by adding an INV ateach output wire. The method further provides testing in parallel thesatisfiability of the original logic circuit, and the satisfiability ofthe dual logic circuit with inverted outputs. Responsive to one of theparallel tests finishing, the other parallel test is caused to alsostop.

In a preferred embodiment the method further comprises responsive totesting that confirms the satisfiability of the original logic circuitand the satisfiability of the dual logic circuit with inverted outputs,configuring the transformed logic for use in a computer system.

An approach taken with the present invention generates two different,but equi-solvable, instances of the same problem. In this scenario,solving both of them in parallel enables a positive computationspeed-up. Indeed, the instance solved first stops the other reducing theruntime. This concept can be used on top of any other checking approachand does not impose much overhead, except having to run two solversinstead of one, which is typically not a problem because multi-cores arewide-spread and computing resources are inexpensive.

In contrast to known parallel checking techniques, the methodologyadopted through the invention creates a different but equi-checkableinstance that has a potentially lower minimum runtime. As a case study,in the section describing preferred embodiments herein under, weinvestigate the impact of the inventive approach on SAT. There, by usingnon-trivial and trivial dualities in sequence, we create a dual SATinstance solvable in parallel with the original one. Experimentalresults show 25% speed-up of SAT, on average, in a concurrent executionscenario. Also, statistical experiments confirmed that the achievedruntime reduction is not of the random variation type.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood in view of the description ofpreferred example embodiments and in reference to the drawings, wherein

FIG. 1 represents a logic circuit example representing the function ƒ=(ab) d+( ab)c+ dc. The basis set is {AND, MAJ, INV}. The gates symbolicrepresentation is shown in the box;

FIG. 2 represents an AND/OR configuration of a three-input MAJ;

FIG. 3 shows logic circuits examples—{AND, OR, INV} logic circuitrepresenting ƒ=ab+ac+a (b+c)+ā(a). {MAJ, INV} logic circuit emulatingthe circuit in (a) using constants (b). {AND, OR, INV} logic circuitsderived from (a) by switching AND/OR operators (c). {MAJ, INV} logiccircuit emulating the circuit in (a) using a fictitious input variable d(d);

FIG. 4 is a graph of a comparison between real inverted and AND/ORswitched logic circuits representing 4-variable Boolean functions. Theon-set size ranges from 0 to 2⁴;

FIG. 5 contains a speculative parallel regular/dual circuit SAT flow;

FIG. 6 is graph showing 1000 randomized SAT runs for regular and dualcircuit;

table I contains switching rules for Tautology/Contradiction Check; and

table 2 contains experimental results for regular vs. dual SAT solving.

DESCRIPTION OF PREFERRED EXAMPLE EMBODIMENTS Notation on Logic Circuits

This section first provides notation on logic circuits. Then, it gives abrief background on tautology checking from an EDA perspective.

A. Notation

A logic circuit is a Directed Acyclic Graph (DAG) representing a Booleanfunction, with nodes corresponding to logic gates and directed edgescorresponding to wires connecting the gates. The on-set of a logiccircuit is the set of input patterns evaluating to true. Analogously,the off-set of a logic circuit is the set of input patterns evaluatingto false. Each logic gate is associated with a primitive Booleanfunction taken from a predefined set of basis logic operators, e.g.,AND, OR, XOR, XNOR, INV, MAJ, MIN etc. Logic operators such as MAJ andMIN represent self dual Boolean functions, i.e., functions whose outputcomplementation is equivalent to inputs complementation. A set of basislogic operators is said to be universal if any Boolean function can berepresented by a logic circuit equipped with those logic gates. Forexample, the basis set {OR, INV} is universal while the basis set {AND,MAJ} is not. FIG. 1 shows a logic circuit for the function

f=(ab)d+(ab)c+dc

over the universal basis set {AND, MAJ, INV}.

B. Tautology Checking

Tautology checking, i.e., verifying whether a logic circuit is true inevery possible interpretation, is an important task in computer scienceand at the core of EDA [5], [7]. Traditionally, tautology checkingsupports digital design verification through combinational equivalencechecking [7]. Indeed, the equivalence between two logic circuits can bedetected by XNOR-ing and checking for tautology. Logic synthesis alsouses tautology checking to

-   -   (i) highlight logic simplifications during optimization [5], [6]        and to    -   (ii) identify matching during technology mapping [8].

On a general basis, many EDA tasks requiring automated deduction aresolved by tautology check routines.

Unfortunately, solving a tautology check problem can be a difficulttask. In its most general formulation, the tautology check problem isco-NP-complete. A straightforward method to detect a tautology is theexhaustive exploration of a function truth table. This naive approachcan declare a tautology only in exponential runtime. More intelligentmethods have been developed in the past. Techniques based onco-factoring trees and binary recursion have been presented in [9].Together with rules for pruning/simplifying the recursion step, thesetechniques reduced the checking runtime on several benchmarks. Anothermethod, originally targeting propositional formulas, is Stalmarck'smethod [10] that rewrites a formula with a possibly smaller number ofconnectives. The derived equivalent formula is represented by tripletsthat are propagated to check for tautology. Unate recursive co-factoringtrees and Stalmarck's method are as bad as any other tautology checkmethod in the worst case but very efficient in real-life applications.With the rise of Binary Decision Diagrams (BDDs) [11], tautology checkalgorithms found an efficient canonical data structure explicitlyshowing the logic feature under investigation [12]. The BDD for atautology is always a single node standing for the logic constant true.Hence, it is sufficient to build a BDD for a logic circuit and verifythe resulting graph size (plus the output polarity) to solve a tautologycheck problem. Unfortunately, BDDs can be exponential in size for somefunctions (multipliers, hidden-weight bit, etc.). In the recent years,the advancements in SAT solving tools [13], [14] enabled more scalableapproaches for tautology checking. Using the trivial duality betweentautology and contradiction, SAT solvers can be used to determine if aninverted logic circuit is unsatisfiable (contradiction) and consequentlyif the original circuit is a tautology. Still, SAT solving is anNP-complete problem so checking for tautology with SAT is difficult ingeneral.

C. Motivation

Tautology checking is a task surfing the edge of today's computingcapabilities. Due to its co-NP-completeness, tautology checkingaggressively consumes computational power when the size of the problemincreases. To push further the boundary of examinable logic circuits, itis important to study new efficient checking methodologies. Indeed, evena narrow theoretical improvement can generate a speed-up equivalent toseveral years of technology evolution.

In the present description, we present a non-trivial duality betweencontradiction and tautology check problems that opens up new efficientsolving opportunities.

Properties of Logic Circuits

In this section, we show properties of logic circuits with regard totheir on-set/off-set balance and distribution. These theoretical resultswill serve as grounds for proving our main assertion in the nextsection.

We initially focus on two universal basis sets: {AND, OR, INV} and {MAJ,INV}. We deal with richer basis sets later on. We first recall a knownfact about majority operators.

Property:

A MAJ operator of n-variables, with n odd, can be configured as an┌n/2┐-variables AND operator by biasing └n/2┘ inputs to logic false andcan be configured as an ┌n/2┐-variables OR operator by biasing └n/2┘inputs to logic true.

For the sake of clarity, an example of a three-input MAJ configurationin AND/OR is depicted by FIG. 2.

Extended at the circuit level, such property enables the emulation ofany {AND, OR, INV} logic circuit by a structurally identical {MAJ, INV}logic circuit. This result was previously shown in [15] where logiccircuit over the basis set {AND, OR, INV} are called AND/OR-INV graphsand logic circuits over the basis set {MAJ, INV} are called MAJ-INVgraphs. An example of two structurally, and functionally, identicallogic circuits over the basis sets {AND, OR, INV} and {MAJ, INV} isdepicted by FIG. 3( a) and FIG. 3( b).

The Boolean function represented in this example is f=ab+ac+a(b+c)+a.MAJ are configured to behave as AND/OR by fixing one input tofalse(F)/true(T), respectively. In place of biasing one input of the MAJwith a logic constant, it is also possible to introduce a fictitiousinput variable connected in regular/inverted polarity to substitutetrue(T)/false(F) constants, respectively. In this way, the functionrepresented is changed but still including the original one when thefictitious input variable is assigned to true. FIG. 3( d) shows a logiccircuit with a fictitious input variable d replacing the logic constantsin FIG. 3( b). The Boolean function represented there is h with propertyha=true=f.

Up to this point, we have shown that {AND, OR, INV} logic circuits canbe emulated by {MAJ, INV} logic circuits configured either by

-   -   (i) logic constants or by    -   (ii) a fictitious input variable.

In the latter case, {MAJ, INV} logic circuits have all inputsassignable.

With no logic constants appearing and all operators being self-dual,this particular class of logic circuits have a perfectly balancedon-set/off-set size. The following theorem formalizes this property.

Theorem 3.1:

Logic circuits over the universal basis set {MAJ, INV}, with all inputsassignable (no logic constants), have |on-set|=2n−1 and |off-set|=2n−1,with n being the number of input variables.

Proof:

MAJ and INV logic operators, with no constants, represent self-dualBoolean functions. In [2], it is shown that self-dual Boolean functionshave an |on-set|=|off-set|=2^(n-1), with n being the number of inputvariables. Also, it is shown in [2] that Boolean functions composed byself-dual Boolean functions are self-dual as well. This is indeed thecase for {MAJ, INV} logic circuits with no constants in input. As thesecircuits represent self-dual Boolean functions, we can assert|on-set|=|off-set|=2^(n-1). Q.E.D.

{MAJ, INV} logic circuits with no constants have a perfectly balancedpartition between on-set size and off-set size. This is the case for theexample in FIG. 3( d). Eventually, we know that by assigning d to truein such example circuit the on-set/off-set balance can be lost. Indeed,with d=true the {MAJ, INV} logic circuit then emulates the original{AND, OR, INV} logic circuit in FIG. 3( a), that could have differenton-set size and off-set size. Still, it is possible to reclaim theperfect on-set/off-set balance by superposing the cases d=true andd=false in the {MAJ, INV} logic circuit. While we know precisely whatthe {MAJ, INV} logic circuit does when d=true, the case d=false is notas evident. We can interpret the case d=false as an inversion in the MAJconfiguration polarity. This means that where a MAJ is configured as anAND (OR) node in d=true, it is instead configured as an OR (AND) node ind=false. In other words, d=false in the {MAJ, INV} logic circuit of FIG.3( d) corresponds to switch AND/OR operator types in the original {AND,OR, INV} logic circuit of FIG. 3( a). The resulting AND/OR switchedcircuit is depicted by FIG. 3( c).

United by a common {MAJ, INV} generalization, {AND, OR, INV} logiccircuits and their AND/OR switched versions share strong propertiesabout on-set/off-set repartition. The following theorem states theirrelation.

Theorem 3.2:

Let A be a logic circuit over the universal basis set {AND, OR, INV}.Let A′ be a modified version of A, with AND/OR operators switched. Thefollowing identities hold |on-set(A)|=|off-set(A′)| and|off-set(A)|=|on-set(A′)|.

Proof:

Say M a {MAJ, INV} logic circuit emulating A using an extra fictitiousinput variable, say d. Md=1 is structurally and functionally equivalentto A, while Md=0 is structurally and functionally equivalent to A′. FromTheorem 3.1 we know that

|on-set(M)|=|off-set(M)|=2^(n-1)=2^(m),

where m is the number of input variables in A and n the number of inputvariables in M, with n=m+1 to take into account the extra fictitiousinput variable in M. We know by construction that

|on-set(Md=1)|+|on-set(Md=0)|=2^(n-1)=2^(m) and

|off-set(Md=1)|+|off-set(Md=0)|=2^(n-1)=2^(m).

Again by construction we know that Md=1 and Md=0 can be substituted by Aand A′, respectively, in all equations. Owing to the basic definition ofA and A′ we have that

|on-set(A)|+|off-set(A)|=2^(m) and

|on-set(A′)|+|off-set(A′)|=2^(m).

Expressing |on-set(A)| as 2^(m)−|on-set(A′)| from the first set ofequations and substituting this term in |on-set(A)|+|off-set(A)|=2m weget 2^(m)−|on-set(A′)|+|off-set(A)|=2^(m) that can be simplified as|off-set(A)|=|on-set(A′)|. This proves the first identity of theTheorem. The second identity can be proved analogously.

Informally, the previous theorem says that by switching AND/OR operatorsin an {AND, OR, INV} logic circuit we swap the on-set and off-set sizes.From a statistical perspective, this is equivalent to invert Pr(A=true)with Pr(A=false), under uniformly random input string of bits. Whilethis also happens with exact logic inversion, here the actualdistribution of the on-set/off-set elements is not necessarilycomplementary. In the next section, we show the implications of thetheoretical results seen so far in tautology and contradiction checkproblems.

From Tautology to Contradiction and Back

Verifying whether a logic circuit is a tautology, a contradiction or acontingency is an important task in logic applications for computers. Inthis section, we show that tautology and contradiction check in logiccircuits are dual and interchangeable problems that do not require exactlogic inversion per se. We start by considering logic circuit over theuniversal basis set {AND, OR, INV} and we consider richer basis setslater on. The following theorem describes the non-trivial dualitybetween tautology and contradiction in {AND, OR, INV} logic circuits.

Theorem 4.1:

let A be a logic circuit over the universal basis set {AND, OR, INV}representing a tautology (contradiction). The logic circuit A′, obtainedby switching AND/OR operations in A, represents a contradiction(tautology).

Proof:

if A represents a tautology then

|on-set(A)|=2^(m) and

|on-set(A)|=0

with m being the number of inputs. Owing to Theorem 3.2

|on-set(A′)|=|off-set(A)|=0 and

|off-set(A′)|=|on-set(A)|=2^(m).

It follows that A′ is a contradiction. Analogous reasoning holds forcontradiction to tautology transformation. Q.E.D.

Switching AND/ORs in an {AND, OR, INV} logic circuit is strictlyequivalent to logic inversion only for tautology and contradiction. Inthe other cases, A and A′ are not necessarily complementary. We giveempirical evidences about this fact hereafter. FIG. 4 depicts theobtained results in a graph chart. We examined 17 random Booleanfunctions of four input variables, with on-set size ranging from 0(contradiction) to 16 (tautology). We first compared the on-set size ofthe real inverted logic circuits with the on-set size of the AND/ORswitched circuits. As expected, Theorem 3.2 holds and switching AND/ORoperators results in exchanging the on-set and off-set sizes. This alsohappens with the real inverted circuits, but in that case also theactual on-set/off-set elements distribution is complementary. To verifywhat is the on-set/off-set elements distribution in general, we define adistance metric between the real inverted and AND/OR switched circuits.The distance metric is computed in two steps. First, the truth tables ofthe circuits are unrolled, using the same input order, and representedas binary strings. Second, the distance metric is measured as theHamming distance 3 between those binary strings. For tautology andcontradiction extremes the distance metric between AND/OR switchedcircuits and real inverted circuits is 0, as obvious consequence ofTheorem 4.1. For other circuits, real inverted and AND/OR switchedcircuits are different, with distance metric ranging between 2 and 10.

As a practical interpretation of the matter discussed so far, we can getan answer for a tautology (contradiction) check problem by working on afunctionally different and non-complementary structure than the originalone under test. We explain hereafter why this fact is interesting.Suppose that the logic circuit we want to check is a contingency butalgorithms for tautology (contradiction) are not efficient on it. If wejust invert the outputs of this logic circuit and we run algorithms forcontradiction (tautology) then we would likely face the same difficulty.However, if we switch AND/ORs in the logic circuit we get a functionallydifferent and non-complementary structure. In this case, algorithms forcontradiction (tautology) do not face by construction the samecomplexity. Exploiting this property, it is possible to speed-up atraditional tautology (contradiction) check problem. Still, Theorem 4.1guarantees that if the original circuit is a tautology (contradiction)then the AND/OR switched version is a contradiction (tautology)preserving the checking correctness.

Recalling the example in FIG. 3( a), the original logic cir-cuitrepresents a tautology. Consequently, the logic circuit in FIG. 3( c)represents a contradiction. These properties are verifiable by hand asthe circuits considered are small. For an example which is acontingency, consider the {AND, OR, INV} circuit realization forf=ab′+c′ (contingency). By switching AND/ORs, we get g=(a+b′) c′ whichis different from both f or f′, as predicted.

We now consider logic circuits with richer basis set functions than just{AND, OR, INV}. Our enlarged basis set includes {AND, OR, INV, MAJ, XOR,XNOR} logic operators. Other operators can always be decomposed intothis universal basis set, or new switching rules can be derived. In thefollowing, we extend the applicability of Theorem 4.1.

Theorem 4.2:

let A be a logic circuit over the universal basis set {AND, OR, INV,MAJ, XOR, XNOR} representing a tautology (contradiction). The logiccircuit A′, obtained by switching logic operators in A as per Table I,represents a contradiction (tautology).

Proof:

in order to prove the theorem, we need to show the switching rules justfor XOR, XNOR and MAJ operators. AND/OR switching is already proved byTheorem 4.1. Consider the XOR operator decomposed in terms of {AND, OR,INV}:

f=a⊕b=ab′+a′b.

Applying the duality in Theorem 4.1 we get

g=(a+b′)(a′+b)

that is indeed equivalent to a XNOR operator. This proves the XOR toXNOR switching and vice versa. Analogously, consider the MAJ operatordecomposed in terms of {AND, OR, INV}:

f=ab+ac+bc.

Applying the duality in Theorem 4.1 we get

g=(a+b)(a+c)(b+c)

that is still equivalent to a MAJ operator. Hence, MAJ operators do notneed to be modified. Q.E.D.

Note that in a data structure for a computer program, the operatorswitching task does not require actual pre-processing of the logiccircuit. Indeed, each time that a node in the DAG is evaluated anexternal flag word determines if the regular or switched operator typehas to be retrieved from memory.

In the current section, have we shown a non-trivial duality betweencontradiction and tautology check. In the next section, we study itsapplication on Boolean satisfiability.

EXPERIMENTAL RESULTS

In this section, we exercise our non-trivial duality in BooleanSATisfiability (SAT) problems. First, we describe how to use thetautology/contradiction duality to generate a second (dual)equi-satisfiable SAT instance. Second, we demonstrate that the dualinstance can be solved faster than the regular one and the correspondingruntime reduction is not of the random variation type. Third, and last,we show experimental results for a concurrent regular/dual SAT executionscenario.

A. Boolean SAT and Tautology/Contradiction Duality

The Boolean SAT problem consists of determining whether there exists ornot an interpretation evaluating to true a Boolean formula or circuit.The Boolean SAT problem is reciprocal to a check for contradiction. Whencontradiction check fails then Boolean SAT succeeds while whencontradiction check succeeds then Boolean SAT fails. Instead of checkingfor Boolean SAT or for contradiction, one can use a dual transformationin the circuit and check for tautology. Such transformation can beeither

-   -   (i) non-trivial, i.e., switching logic operators in the circuit        as per Table I; or    -   (ii) trivial, i.e., output complementation.

If we use twice any dual transformation, we go back to the originalproblem domain (contradiction, SAT). Note that if we use twice the samedual transformation (trivial-trivial or non-trivial-non-trivial) weobtain back exactly the original circuit. Instead, if we apply twodifferent dual transformations in sequence (trivial-non-trivial ornon-trivial-trivial) we obtain an equi-satisfiable but not necessarilyequivalent circuit.

We use the latter approach to generate from the regular a secondequi-satisfiable circuit, which we call the dual circuit. This isillustrated in FIG. 5 wherein an arrow points away to a switching rulestable in which rules from Table 1 are applied to the regular (logic)circuit and the dual (logic) circuit obtained as a result.

The dual circuit SAT—see the two tooth wheels entitled “Solver” and“SAT” next to the Dual circuit—is solved in parallel with the regularcircuit—see the two tooth wheels entitled “Solver” and “SAT” next to thearrow arriving from the Regular circuit—in a first finishing winsspeculative strategy.

FIG. 5 depicts the corresponding flow as a whole.

We generate the dual circuit by first applying our non-trivial duality(switching rules in Table I) and finally complementing the outputs(trivial duality). Note that these operations ideally require no (orvery little) computational overhead, as explained previously.

B. Verification of SAT Solving Advantage on the Dual Circuit

In our first set of experiments we focused on verifying whether the dualcircuit can be easier to satisfy than the regular circuit. For thispurpose, we modified MiniSat-C v1.14.1 [16] to read circuits in AIGERformat [18] and to encode them in CNF internally via Tseitintransformation. The dual circuit is generated online during reading if aswitch “−p” is given. We considered a large circuit (0.7 M nodes) over1000 randomized (pseudo-random number generator seed) runs. FIG. 6 showsthe runtime distributions for dual and regular SAT.

The dual runtime distribution is clearly left-shifted (but partiallyoverlapping) with respect to the regular runtime distribution. Thisconfirms that (i) the dual circuit can be solved faster than the regularone and (ii) the runtime reduction is not of the random variation type.

C. Results for Concurrent Regular/Dual SAT Execution

In our second set of experiments (downloadable at [19]) we used ABC tool[17] to test our dual approach together with advanced techniques tospeed-up SAT. Our custom set of benchmarks is derived by (i) unfoldingSAT sequential problems (ii) encoding combinational equivalence checkproblems. All benchmarks are initially described in Verilog as a netlistof logic gates over the basis {AND, OR, INV, XOR, XNOR, MAJ}. The dualcircuits are obtained by applying switching rules in Table I andinverting the output. The ABC script to read and run SAT on thesebenchmarks is:

read library.genlib;r −m input.v; st;write out.aig;&r out.aig;

&ps;

&write cnf −K 4 out.cnf;dsat −p out.cnf.

Apart from standard I/O commands, note that

-   -   &write cnf −K 4 out.cnf        generates a CNF using a technology mapping procedure and    -   dsat −p        calls MiniSat with variable polarity alignment.

Table II shows results for regular vs. dual SAT solving with our setup.For about half of the benchmarks ( 7/13) the dual instance concludedfirst while for the remaining ones ( 6/13) the regular instance wasfaster. The total regular runtime is quite close to the total dualruntime (just 6% of deviation). However, considering here thespeculative parallel SAT flow in FIG. 5, we can ideally reduce the totalruntime by about 25%. Note that this is an ideal projection into aparallel execution environment, with no overhead. We experimentallyverified that the average overhead can be small (few percentage points)thanks to the intrinsic independence of the two tasks.

CONCLUSION

In this description, we have shown a non-trivial duality betweentautology and contradiction check to speed up circuit SAT. On the onehand, tautology check determines if a logic circuit is true for allinput combinations. On the other hand, contradiction check determines ifa logic circuit is false for all input combinations. A trivialtransformation of a (tautology, contradiction) check problem into a(contradiction, tautology) check problem is the inversion of all theoutputs in a logic circuit. In this work, we proved that exact logicinversion is not necessary. By switching logic operator types in a logiccircuit, following the rules presented in this paper, we can selectivelyexchange tautologies with contradictions. Our approach is equivalent tologic inversion just for tautology and contradiction extreme points. Itgenerates non-complementary logic circuits in the other cases. Suchproperty enables computing benefits when an alternative butequi-solvable instance is easier to solve than the original one. As acase study, we studied the impact on SAT. There, our methodologygenerated a dual SAT instance solvable in parallel with the originalone. This concept can be used on top of any other SAT approach and doesnot impose much overhead, except having to run two solvers instead ofone, which is typically not a problem because multi-cores are widespreadand computing resources are inexpensive. Experimental results shown 25%speed-up of SAT in a concurrent execution scenario.

REFERENCES

-   [1] G. De Micheli, Synthesis and Optimization of Digital Circuits,    McGraw-Hill, New York, 1994.-   [2] T. Sasao, Switching Theory for Logic Synthesis, Springer, 1999.-   [3] M. R. Garey, D. S. Johnson, Computers and Intractability—A Guide    to the Theory of NP-Completeness. W. H. Freeman and Company, 1979.    [4] A. E. Hyvarinen, et al., Incorporating clause learning in    grid-based randomized SAT solving, Journal on SAT (JSAT) 6, 223-244,    2009.-   [5] R. K. Brayton, Logic minimization algorithms for VLSI synthesis,    Vol. 2. Springer, 1984.-   [6] R. Rudell, A. Sangiovanni-Vincentelli Multiple-valued    Minimization far PLA Optimization, IEEE Trans. on CAD of ICs and    Syst. 6.5: 727-750, 1987-   [7] G. Hachtel, F. Somenzi, Logic synthesis and verification    algorithms. Springer, 2006.-   [8] L. Benini, G. De Micheli, A survey of Boolean matching    techniques for library binding, ACM Transaction on DAES (TODAES),    2(3), 193-226, 1997.-   [9] G. D. Hachtel, M. J. Reily, Verification algorithms for VLSI    synthesis, IEEE Trans. on CAD of ICs and Syst. 7.5: 616-640, 1980-   [10] G. Stalmarck, A system for determining propositional logic    theorems by applying values and rules to triplets that are generated    from a formula, Swedish Patent No. 467,076 (approved 1992); U.S.    Pat. No. 5,276,897 (approved 1994); European Patent No. 403,454    (approved 1995).-   [11] R. E. Bryant, Graph-based algorithms for Boolean function    manipulation, IEEE Trans. on Comp., C-35(8): 677-691, 1986.-   [12] S. Malik, A. R. Wang, R. K. Brayton, A.    Sangiovanni-Vincentelli, Logic verification using binary decision    diagrams in a logic synthesis environment, Proc. ICCAD, 1988.-   [13] C. P. Gomes, H. Kautz, A. Sabharwal, B. Selman, Satisfiability    solvers, Handbook of Knowledge Representation 3 (2008): 89-134.-   [14] http://www.satcompetition.org-   [15] L. Amaru, P.-E. Gaillardon, G. De Micheli, Majority-Inverter    Graph: A Novel Data-Structure and Algorithms for Efficient Logic    Optimization, Proc. DAC, 2014.-   [16] MiniSat SAT solver available online at    http://minisat.se/MiniSat.html-   [17] Berkeley Logic Synthesis and Verification Group, ABC: A System    for Sequential Synthesis and Verification,    http://www.eecs.berkeley.edu/alanmi/abc/-   [18] AIGER benchmarks available online at http://fmv.jku.at/aiger/.-   [19] http://lsi.epfl.ch/DUALSAT

1. A method for transforming a tautology check of an original logiccircuit into a contradiction check of the original logic circuit andvice versa, the method comprising: interpreting the original logiccircuit in terms of AND, OR, MAJ, MIN, XOR, XNOR, INV original logicoperators; transforming the original circuit obtained from theinterpreting, into a dual logic circuit enabled for a checking ofcontradiction in place of tautology and vice versa, by providing a setof switching rules configured to switch each respective one of theoriginal logic operators INV, AND, OR, MAJ, XOR, XNOR, MIN into arespective switched logic operator INV, OR, AND, MAJ, XNOR, XOR, MIN;and complementing outputs of the original circuit by adding an INV ateach output wire; testing in parallel the satisfiability of the originallogic circuit, and the satisfiability of the dual logic circuit withinverted outputs; and responsive to one of the parallel tests finishing,causing the other parallel test to also stop.
 2. The method of claim 1,further comprising responsive to testing that confirms thesatisfiability of the original logic circuit and the satisfiability ofthe dual logic circuit with inverted outputs, configuring thetransformed logic for use in a computer system.